The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-266152 filed on Sep. 20, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, and more particularly, to a semiconductor devices such as nonvolatile memory or MOS transistor in which its tunneling oxide film is an oxy-nitride film and at least a part of its control gate is a silicide film or a metal film with a high melting point, and its manufacturing method, which are applicable to NAND EEPROM (electrically erasable and programmable read-only memory), for example.
2. Related Background Art
FIG. 1 is a plan view that shows general configuration of a cell array in a NAND flash memory, and FIG. 2 is a circuit diagram of the cell array of the NAND flash memory shown in FIG. 1.
The cell array of the NAND flash memory shown in FIGS. 1 and 2 is composed of cell transistors CT1, CT2, . . . , CTn in which a plurality of n-channel MOS transistors each having a floating gate and a control gate are connected in series; a selection transistor ST1 in form of an n-channel MOS transistor connected between the drain at one end of the serially connected cell transistors CT1, CT2, . . . , CTn and a bit line BL; a selection transistor ST2 in form of an n-channel MOS transistor connected between the source at the other end of the serially connected cell transistors CT1, CT2, . . . , CTn and a source line GND; selection lines SL1 and SL2 connected to control gates SG1 and SG2 of the selection transistors ST1 and ST2, respectively; and word lines WL1, WL2, . . . , WLn connected to control gates CG1, CG2, . . . , CGn of the cell transistors CT1, CT2, . . . , CTn. The transistors are made in a common well of a common substrate, and the selection line SL1, word lines WL1, WL2, . . . , WLn and selection line SL2 are arranged in sequence substantially in parallel in the direction of rows. The other ends of the word lines WL1, WL2, . . . , WLn are connected to a connection pad for connection to a peripheral circuit via aluminum wirings.
Explained below is a structure of a cell array of a conventional NAND flash memory and its manufacturing method with reference to a cross-sectional view of a portion corresponding to the B-Bxe2x80x2 line of FIG. 1.
FIG. 3 is the cross-sectional view that shows the structure of the cell array in the conventional NAND flash memory.
The cell array of the conventional NAND flash memory shown in FIG. 3 is composed of a silicon substrate 1; a first gate insulating film 3 in form of an oxy-nitride film stacked on the top surface of the silicon substrate 1; floating gates 4 in form of a polycrystalline silicon film stacked on predetermined locations of the first gate insulating film 3; a second gate insulating film 5 in form of a silicon oxide film stacked on the floating gates 4; control gates made of a polycrystalline silicon film 6 and a tungsten silicide film 7 sequentially stacked on the second gate insulating film 5; an oxide film 8 stacked on the tungsten silicide film 7; a secondary oxide film 11 in form of a silicon oxide film stacked on side surfaces of the oxide film 8, the tungsten silicide film 7, and the polycrystalline silicon film 6, the second gate insulating film 5, the polycrystalline silicon film 4 and top surface of the oxide film 8; and diffusion layers 12 formed in predetermined regions of the top surface portion of the silicon substrate 1.
The cell array of the above conventional NAND flash memory is made by the following manufacturing method.
FIGS. 4A through 4G are cross-sectional views of the cell array of the conventional NAND flash memory shown in FIG. 3 under a process of its manufacturing method.
First as shown in FIG. 4A, the silicon oxide film 2, 7 nm thick, is made on the silicon substrate 1 by thermal oxidation.
After the silicon oxide film 2 is formed, as shown in FIG. 4B, the silicon oxide film 2 is nitrified by using ammonium gas (NH3) and next oxidized to form an oxy-nitride film 3. This oxy-nitride film 3 serves as a first gate oxide film, and it is normally called a tunneling oxide film.
After the oxy-nitride film 3 is made, as shown in FIG. 4C, the polycrystalline silicon film 4, 200 nm thick and doped with phosphorus as an impurity, is formed on the oxy-nitride film 3 by LPCVD. The polycrystalline silicon film 4 is later processed to a first gate electrode, and it is normally called a floating gate. After the polycrystalline silicon film 4 is made, the second gate insulating film 5, 120 nm thick, is stacked on the polycrystalline silicon film 4 by LPCVD. After the second gate insulating film 5 is formed, the polycrystalline silicon film 6 doped with phosphorus as an impurity is stacked on the second gate insulating film 5 by LPCVD, and the tungsten silicide film 7, which is a low-resistance wiring material, is further stacked on the polycrystalline silicon film 6 by CVD. The polycrystalline silicon film 6 and the tungsten silicide film 7, altogether, form the second gate electrode which is normally called a control gate. After the tungsten silicide film 7 is formed, the oxide film 8 is made on the tungsten silicide film 7.
After the oxide film 8 is made, as shown in FIG. 4D, a photo resist 9 is spread on the oxide film 8 and processed into a predetermined pattern by photo-etching. Then, using the photo resist 9 as a mask, the oxide film 8 is processed into the same pattern by RIE or other dry etching. After the oxide film 8 is formed, the photo resist 9 is removed.
After removal of the photo resist 9, as shown in FIG. 4E, using the oxide film 8 as a mask, the tungsten silicide film 7, the polycrystalline silicon film 6, the second gate insulating film 5 and the polycrystalline silicon film 4 are selectively removed sequentially in the vertical direction by anisotropic etching using RIE or other dry etching technique.
After that, for the purpose of preventing leak current at the gate end, improving surface resistance to voltage of the peripheral circuit MOS transistor, i.e. resistance to voltage of the gate insulating film and recovering damages introduced into the gate oxide film through the gate electrode by RIE, and for other purposes, the silicon oxide film 11 is stacked on side surfaces of the oxide film 8, the tungsten silicide film 7, the polycrystalline silicon film 6, the second gate insulting film 5 and the polycrystalline silicon film 4 and the top surface of the oxide film 8 as shown in FIG. 4F. Normally, this oxidation process is called secondary oxidation process, and the oxide film 11 made in this step is called secondary oxide film.
After the secondary oxide film 11 is made, as shown in FIG. 4G, for the purpose of making source regions and drain regions, an impurity is ion-implanted into the silicon substrate 1 and activated by annealing to create diffusion layers 12 and make memory transistors. As a result, the structure of the cell array of the conventional NAND flash memory shown in FIG. 3 is obtained.
However, in the case where an oxy-nitride film is used as the tunneling oxide film 3 like the cell array of the conventional NAND flash memory as discussed above, nitrogen concentration of the tunneling oxide film 3 is high, and especially after RIE for gate processing, nitrogen concentration of the tunneling oxide film 3 becomes high along the circumferential portion of the bottom of the floating gate 4. As a result, as shown in FIGS. 4F and 4G, it becomes difficult to make the secondary oxide film 11 along the circumference portion of the bottom of the floating gate 4, and it invites deterioration of the device property, decrease of the reliability, drop of the production yield, an so on.
On the other hand, if the secondary oxide film 11 is made by wet oxidation exhibiting a high oxidizing function, then the deposition of the secondary oxide film 11 is promoted, but its oxidizing function causes abnormal growth of the tungsten silicide film 7 of the control gate, which in turn damages the second gate insulating film 5 and the first gate oxide film (tunneling oxide film) 3.
It is therefore an object of the invention to provide a semiconductor device and its manufacturing method in which a secondary oxide film can be normally made along the circumferential portion of the bottom of a gate electrode in a semiconductor device using an oxy-nitride film as a tunneling oxide film and a silicide film with a high melting point or a metal film with a high melting point to form at least a part of the gate electrode while preventing abnormal growth of the high-melting-point silicide film or the high-melting-point metal film.
A semiconductor device according to the first configuration of the invention comprises a semiconductor substrate; a gate insulating film in form of an oxy-nitride film formed on a surface of the semiconductor substrate; a gate electrode formed on a predetermined region of the gate insulating film and partly made of a silicide film having a high melting point or a metal film having a high melting point; an electrode protective film formed to cover side surfaces of the gate electrode and lie apart from the gate insulating film; and a secondary oxide film formed on surfaces of the gate insulating film, the gate electrode and the electrode protective film.
A semiconductor device according to the second configuration of the invention comprises a semiconductor substrate; a first gate insulating film in form of an oxy-nitride film formed on a surface of the semiconductor substrate; a first gate electrode formed on a predetermined region of the first gate insulating film; a second gate insulating film formed on the first gate electrode; a second gate electrode formed on the second gate insulating film and partly made of a silicide film having a high melting point or a metal film having a high melting point; an electrode protective film formed to cover side surfaces of the second gate electrode and lie apart from the first gate insulating film; and a secondary oxide film formed on surfaces of the first gate insulating film, the first gate electrode, the second gate insulating film and the second gate electrode.
A manufacturing method of a semiconductor device according to the first configuration of the invention comprises a first step of making a gate insulating film in form of an oxy-nitride film on a surface of a semiconductor substrate; a second step of making a semiconductor layer as a part of a gate electrode on the gate insulating film; a third step of making a silicide film having a high melting point or a metal film having a high melting point as a part of the gate electrode on the semiconductor layer; a fourth step of making a mask member of a pattern of the gate electrode on the silicide film having a high melting point or the metal film having a high melting point; a fifth step of etching the silicide film having a high melting point or the metal film having a high melting point into the pattern of the gate electrode by using the mask member as a mask while maintaining the surface of the gate insulating film covered; a sixth step of making an electrode protective film which covers side surfaces of the silicide film having a high melting point or the metal film having a high melting point, and lies apart from the gate insulating film, while maintaining the surface of the gate insulating film covered; a seventh step of etching the semiconductor layer into the form of the gate electrode by using the electrode protective film as a mask; and an eighth step of making a secondary oxide film by secondary oxidation of surfaces of the gate insulating film, the gate electrode and the electrode protective film.
A manufacturing method of a semiconductor device according to the second configuration of the invention comprises a first step of making a first gate insulating film in form of an oxy-nitride film on a surface of a semiconductor substrate; a second step of making a first semiconductor layer to be processed as a first gate electrode on the first gate insulating film; a third step of making a second gate insulating film on the first semiconductor layer; a fourth step of making a second semiconductor layer as a part of a second gate electrode on the second gate insulating film; a fifth step of making a silicide film having a high melting point or a metal film having a high melting point as a part of the second gate electrode on the second semiconductor layer; a sixth step of making a mask member of a pattern of the first and second gate electrodes on the silicide film having a high melting point or the metal film having a high melting point; a seventh step of etching the silicide film having a high melting point or the metal film having a high melting point into the form of the second gate electrode by using the mask member as a mask, while maintaining the surface of the first gate insulating film covered; an eighth step of making an electrode protective film which covers side surfaces of the silicide film having a high melting point or the metal film having a high melting point, and lies apart from the first gate insulating film, while maintaining the surface of the first gate insulating film covered; a ninth step of etching the portions of the second semiconductor layer, the second gate insulating film and the first semiconductor layer, which remain as a result of etching in the seventh step, into the form of the first and second gate electrodes by using the electrode protective film as a mask; and a tenth step of making a secondary oxide film by secondary oxidation of surfaces of the gate insulating films, the gate electrodes and the electrode protective film.
In the semiconductor device and its manufacturing method according to each configuration of the invention, since the electrode protective film covering side surfaces of the high-melting-point silicide film or the high-melting-point metal film constructing a part of the gate electrode is made prior to deposition of the secondary oxide film, it is possible to make the secondary oxide film to sufficiently recover the damage of the gate insulating film (the first gate insulating film (the tunneling oxide film)) caused by gate processing while preventing abnormal oxidation of the high-melting-point silicide film or the high-melting-point metal film. At the same time, it is also possible to round gate edges along the circumferential portions of bottoms of the gate electrodes (the first gate electrodes) and thereby prevent concentration of the electric field. Therefore, device property, reliability and production yield can be improved. Additionally, since the electrode protective film covering side surfaces of the high-melting-point silicide film or the high-melting-point metal film is formed to be apart from the gate insulating film (the first gate insulating film (the tunneling oxide film)) and lie only over the gate electrodes (the first gate electrodes), deterioration of the gate insulating film (the first gate insulating film (the tunneling oxide film)) by moisture contained in the electrode protective film does not occur, and the current flowing in the gate insulating film (the first gate insulating film (the tunneling oxide film)) can be stabilized.